Invention Application
- Patent Title: Work Conserving, Load Balancing, and Scheduling
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Application No.: US15089522Application Date: 2016-04-02
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Publication No.: US20170286157A1Publication Date: 2017-10-05
- Inventor: Joseph R. Hasting , William G. Burroughs
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06F9/50

Abstract:
A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.
Public/Granted literature
- US10552205B2 Work conserving, load balancing, and scheduling Public/Granted day:2020-02-04
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