Invention Application
- Patent Title: Multiple Shielding Trench Gate FET
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Application No.: US15622869Application Date: 2017-06-14
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Publication No.: US20170288052A1Publication Date: 2017-10-05
- Inventor: Hideaki Kawahara , Seetharaman Sridhar , Christopher Boguslaw Kocon , Simon John Molloy , Hong Yang
- Applicant: Texas Instruments Incorporated
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/28 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/40

Abstract:
A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
Public/Granted literature
- US10541326B2 Multiple shielding trench gate FET Public/Granted day:2020-01-21
Information query
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