Invention Application
- Patent Title: TERMINATION SCHEMES FOR MULTI-RANK MEMORY BUS ARCHITECTURES
-
Application No.: US15368445Application Date: 2016-12-02
-
Publication No.: US20170351625A1Publication Date: 2017-12-07
- Inventor: Tin Tin Wee , Thomas Bryan
- Applicant: QUALCOMM Incorporated
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G11C11/401 ; G06F9/445
Abstract:
A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.
Public/Granted literature
- US09984011B2 Termination schemes for multi-rank memory bus architectures Public/Granted day:2018-05-29
Information query
