- 专利标题： METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
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申请号： US15623978申请日： 2017-06-15
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公开(公告)号： US20180005980A1公开(公告)日： 2018-01-04
- 发明人: Basil Milton , Wei Qin
- 申请人： Kulicke and Soffa Industries, Inc.
- 主分类号： H01L23/00
- IPC分类号： H01L23/00
摘要：
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
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