Invention Application
- Patent Title: POST-RETIRE SCHEME FOR TRACKING TENTATIVE ACCESSES DURING TRANSACTIONAL EXECUTION
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Application No.: US15699823Application Date: 2017-09-08
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Publication No.: US20180011748A1Publication Date: 2018-01-11
- Inventor: Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
- Applicant: Intel Corporation
- Main IPC: G06F9/52
- IPC: G06F9/52 ; G06F9/38 ; G06F9/30

Abstract:
A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.
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