Invention Application
- Patent Title: DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC
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Application No.: US15674763Application Date: 2017-08-11
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Publication No.: US20180012760A1Publication Date: 2018-01-11
- Inventor: Jiehui SHU , Daniel JAEGER , Garo Jacques DERDERIAN , Haifeng SHENG , Jinping LIU
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L27/11

Abstract:
Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.
Information query
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