• Patent Title: Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits
  • Application No.: US15718375
    Application Date: 2017-09-28
  • Publication No.: US20180018416A1
    Publication Date: 2018-01-18
  • Inventor: Mahesh A. IyerVasudeva M. Kamath
  • Applicant: Intel Corporation
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits
Abstract:
A method for performing rewind functional verification includes identifying state variables that model the number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.
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