公开(公告)号：US20220004688A1

公开(公告)日：2022-01-06

申请号：US17481038

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Rajiv Mongia ,  Ravi Gutala ,  Kaushik Chanda ,  Gurvinder Tiwana ,  Vadali Mahadev ,  Mahesh A. Iyer

IPC: G06F30/337 ,  G06F30/343

Abstract: Systems and methods are provided for generating a circuit design for an integrated circuit using a circuit design tool. The circuit design tool determines maximum junction temperatures for circuit blocks in the circuit design for the integrated circuit. The circuit design tool determines defects values for the circuit blocks using the maximum junction temperatures for the circuit blocks. The circuit design tool determines a defects value for the circuit design based on the defects values for the circuit blocks. The circuit design tool determines a maximum junction temperature for the circuit design based on a comparison between the defects value for the circuit design and a target defects value for the circuit design. The circuit design tool can dynamically reconfigure configurable logic circuit blocks to improve the power, the performance, and the thermal profile to achieve an optimal junction temperature per circuit block.

公开(公告)号：US20210383049A1

公开(公告)日：2021-12-09

申请号：US17406534

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Ning Cheng ,  Xiangyong Wang ,  Mahesh A. Iyer

IPC: G06F30/392 ,  G06F30/34 ,  G06F30/394 ,  G06F30/398

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

公开(公告)号：US10318686B2

公开(公告)日：2019-06-11

申请号：US15391511

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Shounak Dhar ,  Mahesh A. Iyer ,  Love Singhal ,  Nikolay Rubanov ,  Saurabh Adya

IPC: G06F17/50

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed.

公开(公告)号：US20190146028A1

公开(公告)日：2019-05-16

申请号：US16232023

申请日：2018-12-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3193

Abstract: A method includes mapping an AMC into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

公开(公告)号：US20190044518A1

公开(公告)日：2019-02-07

申请号：US16019297

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer

IPC: H03K19/177 ,  G06F17/50

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

公开(公告)号：US20190043782A1

公开(公告)日：2019-02-07

申请号：US15981081

申请日：2018-05-16

Applicant: Intel Corporation

Inventor： Sumita Basu ,  Aravind Dasu ,  Mahesh A. Iyer

IPC: H01L23/427 ,  F28D15/04 ,  F28D15/06 ,  H01L25/065 ,  G06F17/50 ,  H01L23/34

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

公开(公告)号：US10181001B2

公开(公告)日：2019-01-15

申请号：US15422971

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Mahesh A. Iyer

IPC: G06F17/50 ,  G06F13/42

Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.

公开(公告)号：US20240020449A1

公开(公告)日：2024-01-18

申请号：US18475512

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  Deshanand P. Singh ,  Gregg William Baeckler ,  Mahesh A. Iyer ,  Michael Kinsner ,  Chengping Liang ,  Victor Tzi-on Zhang

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design. For example, a design may be mapped to one or more macros in the library, and the one or more macros may be placed into and routed between a portion of a region, one region, one or more regions of the integrated circuit device to implement the design. Since the macros may be pre-compiled, compilation time experienced by the designer may correspond to the placement and routing of the one or more macros, which may be less than compilation time for fine-grained operations. The pre-compiled logic within the macros may be set using a lookup table mask to set and/or adjust a functionality of the macro. Additionally or alternatively, the place and route operation may be performed at finer granularities to reduce bottle necks.

公开(公告)号：US20230237231A1

公开(公告)日：2023-07-27

申请号：US18191785

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  Michael Kinsner ,  Gabriel Quan ,  Victor Tzi-on Zhang ,  Mahesh A. Iyer ,  Chengping Liang ,  Deshanand P. Singh

IPC: G06F30/347 ,  G06F30/31

CPC classification number: G06F30/347 ,  G06F30/31

Abstract: Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.

公开(公告)号：US20230237230A1

公开(公告)日：2023-07-27

申请号：US18191789

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  Byron Sinclair ,  Deshanand P. Singh ,  Scott Jeremy Weber ,  Anandh Venkateswaran ,  Mahesh A. Iyer

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347 ,  G06F2119/12

Abstract: Systems or methods of the present disclosure may provide a library including multiple personas that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more personas to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The personas may be loaded into one or more regions of the integrated circuit device to realize the design. That is, the design may be realized by one persona may be implemented across multiple regions, one region may be configured by multiple personas, one persona configuring one region, or any combination thereof. Additionally or alternatively, the integrated circuit device may include networks-on-chip to improve data routing between the regions.