Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC) The ADC includes a digital sensor responsive to an analog field quantity The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The fitter low pass filters and decimates tea lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.