Invention Application
- Patent Title: LIGHT-WEIGHT CACHE COHERENCE FOR DATA PROCESSORS WITH LIMITED DATA SHARING
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Application No.: US15264804Application Date: 2016-09-14
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Publication No.: US20180074958A1Publication Date: 2018-03-15
- Inventor: Nuwan Jayasena , Michael Boyer
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G06F12/0811
- IPC: G06F12/0811

Abstract:
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
Public/Granted literature
- US10042762B2 Light-weight cache coherence for data processors with limited data sharing Public/Granted day:2018-08-07
Information query
IPC分类: