Invention Application
- Patent Title: CYCLICALLY INTERLEAVED XOR ARRAY FOR ERROR RECOVERY
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Application No.: US15346103Application Date: 2016-11-08
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Publication No.: US20180129430A1Publication Date: 2018-05-10
- Inventor: Jingyu Kang , Chung-Li Wang , Cai Wang , Yibo Zhang
- Applicant: SK Hynix Memory Solutions Inc.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10 ; G11C29/52 ; H03M13/13 ; H03M13/27

Abstract:
Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.
Public/Granted literature
- US09996285B2 Cyclically interleaved XOR array for error recovery Public/Granted day:2018-06-12
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