- 专利标题: Field Programmable Logic Array
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申请号: US15546694申请日: 2015-01-28
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公开(公告)号: US20180278254A1公开(公告)日: 2018-09-27
- 发明人: Teruaki SAKATA , Tsutomu YAMADA , Teppei HIROTSU
- 申请人: Hitachi, Ltd.
- 国际申请: PCT/JP2015/052258 WO 20150128
- 主分类号: H03K19/177
- IPC分类号: H03K19/177 ; G06F11/10 ; G11C29/52 ; G01R31/317
摘要:
To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.
公开/授权文献
- US10425081B2 Field programmable logic array 公开/授权日:2019-09-24
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