- 专利标题: DELAY LINE CIRCUIT AND METHOD OF OPERATING THE SAME
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申请号: US16005435申请日: 2018-06-11
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公开(公告)号: US20180294803A1公开(公告)日: 2018-10-11
- 发明人: Ming-Chieh HUANG , Chan-Hong CHERN , Tsung-Ching (Jim) HUANG , Chih-Chang LIN , Tien-Chun YANG
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 主分类号: H03K5/134
- IPC分类号: H03K5/134 ; H03K5/14 ; H03K5/00
摘要:
A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
公开/授权文献
- US10367491B2 Delay line circuit and method of operating the same 公开/授权日:2019-07-30
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