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    PHOTODETECTOR AND METHOD FOR FORMING THE SAME
    2.
    发明申请
    PHOTODETECTOR AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220352399A1

    公开(公告)日：2022-11-03

    申请号：US17864725

    申请日：2022-07-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chan-Hong CHERN

    IPC分类号： H01L31/0352 ,  H01L31/18 ,  H01L31/0224 ,  H01L31/105

    摘要： A photodetector is provided. The photodetector includes a bottom electrode region in a semiconductor layer, a light absorption material in the semiconductor layer, and a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer. The first buffer layer includes, from bottom to top, a first Si layer, a first SiGe layer, a second Si layer, and a second SiGe layer. A first atomic percentage of Ge in the first SiGe layer is less than a second atomic percentage of Ge in the second SiGe layer. The photodetector further includes a top electrode region over the light absorption material.

    INPUT/OUTPUT CIRCUIT
    4.
    发明申请
    INPUT/OUTPUT CIRCUIT 审中-公开
    输入/输出电路

    公开(公告)号：US20160359475A1

    公开(公告)日：2016-12-08

    申请号：US15244152

    申请日：2016-08-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chan-Hong CHERN ,  Tsung -Ching HUANG ,  Chih-Chang LIN ,  Ming-Chieh HUANG ,  Fu-Lung HSUEH

    IPC分类号： H03K5/1534 ,  H03K17/687

    CPC分类号： H03K5/1534 ,  H03K5/131 ,  H03K17/167 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2005/00019 ,  H03K2005/00058

    摘要： A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.

    摘要翻译： 电路包括具有第一电压电平的第一功率节点和输出节点。 耦合在第一功率和输出节点之间的驱动器晶体管分别响应于第一和第二输入信号边缘类型而导通和截止。 驱动晶体管源与第一功率节点耦合。 竞争电路包括基于输出节点信号产生反馈信号的转换速率检测电路和驱动晶体管漏极与第二电压之间的竞争晶体管。 竞争晶体管栅极基于反馈信号接收控制信号。 如果输出节点信号响应于第一输入信号边缘类型上升，则第二电压具有小于第一电压电平的电平，并且如果输出节点信号响应于第一输入信号边缘类型而降低，则大于第一电压电平。

    LATCH CIRCUIT AND METHOD OF OPERATING THE LATCH CIRCUIT
    5.
    发明申请
    LATCH CIRCUIT AND METHOD OF OPERATING THE LATCH CIRCUIT 有权
    锁存电路和操作电路的方法

    公开(公告)号：US20160248408A1

    公开(公告)日：2016-08-25

    申请号：US14630941

    申请日：2015-02-25

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Tsung-Ching (Jim) HUANG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tien-Chun YANG

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356104

    摘要： A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.

    摘要翻译： 锁存电路包括第一输入节点，第二输入节点，第一输出节点，第二输出节点，耦合在第一输出节点和第二输出节点之间的第一开关装置，以及与第一输入端耦合的第一放大电路 节点，第二输入节点，第一输出节点和第二输出节点。 第一开关装置被配置为响应于时钟信号的第一状态而导通，并且响应于时钟信号的第二状态而被关断。 第一放大电路被配置为响应于时钟信号的第一状态，基于第一输入节点和第二输入节点的电压电平引起第一开关装置两端的电压差。

    DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT
    6.
    发明申请
    DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT 有权
    具有可变延迟线单元的延迟线电路

    公开(公告)号：US20160065194A1

    公开(公告)日：2016-03-03

    申请号：US14939255

    申请日：2015-11-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tsung-Ching HUANG ,  Chih-Chang LIN ,  Fu-Lung HSUEH

    IPC分类号： H03K5/14

    CPC分类号： H03K5/14 ,  H03K5/133 ,  H03K2005/00019 ,  H03K2005/00071

    摘要： A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.

    摘要翻译： 延迟线电路包括多个延迟电路和可变延迟线电路。 多个延迟电路接收输入信号并产生第一输出信号。 第一输出信号对应于延迟输入信号或反相输入信号。 可变延迟线电路接收第一输出信号。 可变延迟线电路包括输入端，输出端，第一和第二路径。 输入端被配置为接收第一输出信号。 输出端被配置为输出第二输出信号。 第一路径包括第一多个逆变器和第一电路。 第二路径包括第二多个反相器和第二电路。 基于从延迟线控制器​​接收的控制信号，接收到的第一输出信号通过第一或第二路径选择性地发送。

    INTEGRATED CIRCUITS WITH RESISTORS
    7.
    发明申请
    INTEGRATED CIRCUITS WITH RESISTORS 有权
    集成电路与电阻

    公开(公告)号：US20140367793A1

    公开(公告)日：2014-12-18

    申请号：US14475058

    申请日：2014-09-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH

    IPC分类号： H01L27/06 ,  H01L29/49 ,  H01L49/02

    CPC分类号： H01L27/0629 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

    摘要： An integrated circuit includes a transistor. The transistor includes a first gate dielectric structure over a substrate, a work-function layer over the first gate dielectric structure, a conductive layer over the work-function layer, and a source/drain (S/D) region adjacent to each sidewall of the first gate dielectric structure. Additionally, the integrated circuit includes a resistor structure. The resistor structure further includes a first doped semiconductor layer over the substrate, wherein a top surface of the resistor structure is substantially planar with a top surface of the transistor.

    摘要翻译： 集成电路包括晶体管。 晶体管包括在衬底上的第一栅极电介质结构，在第一栅极电介质结构上方的功函数层，功函数层上的导电层以及与每个侧壁相邻的源极/漏极（S / D）区域 第一栅介质结构。 此外，集成电路包括电阻器结构。 电阻器结构还包括在衬底上的第一掺杂半导体层，其中电阻器结构的顶表面与晶体管的顶表面基本上是平面的。

    INTEGRATED CIRCUIT LAYOUT
    8.
    发明申请
    INTEGRATED CIRCUIT LAYOUT 有权
    集成电路布局

    公开(公告)号：US20140109033A1

    公开(公告)日：2014-04-17

    申请号：US14134144

    申请日：2013-12-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Li-Chun TIEN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A layout of a portion of an integrated circuit includes first and second cell structures, each including a first or second dummy gate electrode disposed on a first or second boundary of the corresponding first or second cell structure, a first or second edge gate electrode disposed adjacent to the corresponding first or second dummy gate electrode, and a first or second oxide definition (OD) region having a first or second edge. The second boundary faces the first boundary without abutting the first boundary. The first edge of the first OD region is substantially aligned with the closest edge of the first dummy gate electrode or overlaps the first dummy gate electrode. A distance from the first edge gate electrode to the farthest edge of the first dummy gate electrode is greater than the distance from the first edge gate electrode to the first edge of the first OD region.

    摘要翻译： 集成电路的一部分的布局包括第一和第二单元结构，每个单元结构包括布置在相应的第一或第二单元结构的第一或第二边界上的第一或第二虚设栅电极，邻近设置的第一或第二边缘栅电极 到相应的第一或第二伪栅电极，以及具有第一或第二边缘的第一或第二氧化物界定（OD）区域。 第二个边界面临第一个边界，而不会邻接第一个边界。 第一OD区域的第一边缘基本上与第一伪栅电极的最近边缘对准或者与第一伪栅电极重叠。 从第一边缘栅电极到第一虚拟栅电极的最远边缘的距离大于从第一边缘栅电极到第一OD区域的第一边缘的距离。

    TEMPERATURE SENSING CIRCUIT
    10.
    发明申请
    TEMPERATURE SENSING CIRCUIT 有权
    温度感应电路

    公开(公告)号：US20130272340A1

    公开(公告)日：2013-10-17

    申请号：US13915236

    申请日：2013-06-11

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chan-Hong CHERN ,  Steven SWEI

    IPC分类号： G01K7/14

    CPC分类号： G01K7/14 ,  G01K7/01 ,  G01K2219/00

    摘要： A circuit includes a comparator, a first circuit, and a second circuit. The comparator has a first input node and a second input node. The first circuit is configured to output a temperature-dependent voltage at the first input node of the comparator. The first circuit includes a current mirror configured to generate a first reference voltage. The second circuit is configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

    摘要翻译： 电路包括比较器，第一电路和第二电路。 比较器具有第一输入节点和第二输入节点。 第一电路被配置为在比较器的第一输入节点处输出与温度有关的电压。 第一电路包括被配置为产生第一参考电压的电流镜。 第二电路被配置为响应于数字码和第一参考电压在比较器的第二输入节点处输出第二参考电压。