Invention Application
- Patent Title: LOW TEMPERATURE SELECTIVE EPITAXIAL SILICON DEPOSITION
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Application No.: US15951051Application Date: 2018-04-11
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Publication No.: US20180308685A1Publication Date: 2018-10-25
- Inventor: Geetika BAJAJ , Prerna Sonthalia GORADIA , Robert Jan VISSER
- Applicant: Applied Materials, Inc.
- Main IPC: H01L21/02
- IPC: H01L21/02 ; C23C16/24 ; C23C16/455 ; C30B25/02 ; C30B29/06

Abstract:
Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (“SAM”) is used to achieve selective epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate to a self-assembled monolayer (“SAM”) forming molecule to selectively deposit a SAM film on an exposed dielectric material, wherein the substrate comprises the exposed dielectric material and an exposed silicon material. The SAM forming molecule is a chlorosilane molecule. The method further comprises epitaxially and selectively depositing a silicon-containing material layer on the exposed silicon material at a temperature of 400 degrees Celsius or lower. The method further comprises removing the SAM film from the exposed dielectric material.
Information query
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