公开(公告)号：US20240026527A1

公开(公告)日：2024-01-25

申请号：US18224455

申请日：2023-07-20

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Supriya GHOSH ,  Susmit Singha ROY ,  Darshan THAKARE ,  Gopi Chandran RAMACHANDRAN ,  Bhaskar Jyoti BHUYAN ,  Abhijit B. MALLICK

IPC: C23C16/04 ,  C23C16/30 ,  C23C16/56

CPC classification number: C23C16/045 ,  C23C16/30 ,  C23C16/56

Abstract: A method of forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of a diaminosilane, an aminosilane, and a combination thereof. The method includes delivering an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing compound are alternated cyclically to fill the high aspect ratio opening.

公开(公告)号：US20220392810A1

公开(公告)日：2022-12-08

申请号：US17770434

申请日：2020-12-08

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Prerna Sonthalia GORADIA ,  Robert J. VISSER

IPC: H01L21/66 ,  G01B15/04 ,  B05D1/00

Abstract: The enclosed disclosure relates to a method and apparatus for depositing functionalized nanoparticles within a semiconductor structure in order to create a nano-layer capable of enhancing imaging and contrast, The semiconductor structure can include any type of VNAND structure or 3D structure, The nanoparticles are formed in high-aspect ratio trenches of the structure and form a nano-layer. The functionalized nanoparticles comprise synthesized nanoparticles as well as organic molecules. The organic molecules are chosen to selectively bind to certain nanoparticles and surface materials.

公开(公告)号：US20220277936A1

公开(公告)日：2022-09-01

申请号：US17625179

申请日：2020-06-22

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Yogita PAREEK ,  Darshan THAKARE ,  Prerna Sonthalia GORADIA ,  Ankur KADAM ,  Kevin A. PAPKE

IPC: H01J37/32 ,  C23C16/34 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  C23C16/44 ,  C23C16/56 ,  C23C16/50

Abstract: The present disclosure relates to protective multilayer coatings for processing clumbers and processing clumber components. In one embodiment, a multilayer protean e coating includes a metal nitride layer and an oxide layer disposed thereon. In one embodiment, the multilayer protective coating further includes an oxynitride interlayer and/or an oxy fluoride layer. The multilayer protective coating may be formed on a metal alloy or ceramic substrate, such as a processing clumber or a processing clumber component used in tire field of electronic device manufacturing, e.g., semiconductor device manufacturing. In one embodiment, the metal nitride layer and the oxide layer are deposited on the substrate by atomic layer deposition.

公开(公告)号：US20210071300A1

公开(公告)日：2021-03-11

申请号：US16698549

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Yogita PAREEK ,  Prerna Sonthalia GORADIA ,  Ankur KADAM

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/40

Abstract: Embodiments of the disclosure provide methods for fabricating or otherwise forming a protective coating containing cerium oxide on processing chamber surfaces and/or components, such as surfaces which are exposed to a plasma within a processing chamber. In one or more embodiments, a method of forming a protective coating within a processing chamber includes depositing a cerium oxide layer on a chamber surface or a chamber component during an atomic layer deposition (ALD) process. The ALD process includes sequentially exposing the chamber surface or the chamber component to a cerium precursor, a purge gas, an oxidizing agent, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the cerium oxide layer.

公开(公告)号：US20170260618A1

公开(公告)日：2017-09-14

申请号：US15451995

申请日：2017-03-07

Applicant: Applied Materials, Inc.

Inventor： Laksheswar KALITA ,  Prerna A. GORADIA ,  Geetika BAJAJ ,  Yogita PAREEK ,  Yixing LIN ,  Dmitry LUBOMIRSKY ,  Ankur KADAM ,  Bipin THAKUR ,  Kevin A. PAPKE ,  Kaushik VAIDYA

IPC: C23C8/12 ,  C22F1/16 ,  C23C8/16 ,  C25D3/54 ,  C25D5/50

CPC classification number: C23C8/12 ,  C22F1/16 ,  C23C8/02 ,  C23C8/16 ,  C25D3/54 ,  C25D5/18 ,  C25D5/48 ,  C25D5/50 ,  C25D11/08 ,  C25D11/34

Abstract: The present disclosure generally relates to methods of electro-chemically forming yttria or yttrium oxide. The methods may include the optional preparation of a an electrochemical bath, the electrodepositon of yttria or yttrium oxide onto a substrate, removal of solvent form the surface of the substrate, and post treatment of the substrate having the electrodeposited yttria or yttrium oxide thereon.

公开(公告)号：US20240145242A1

公开(公告)日：2024-05-02

申请号：US18384688

申请日：2023-10-27

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Srobona SEN ,  Xuebin LI ,  Joe MARGETIS ,  Provas PAL ,  Gopi Chandran RAMACHANDRAN

IPC: H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/02642 ,  H01L21/02052 ,  H01L21/02532 ,  H01L21/32055

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a blocking layer of molecules is used to achieve selective epitaxial deposition. In one implementation, a method of processing a mixed-surface substrate comprising an exposed dielectric material and an exposed silicon-based material is provided. The method comprises depositing a blocking layer on the exposed dielectric material and epitaxially and selectively depositing a silicon-containing material layer on the exposed silicon-based material at a temperature of 400 degrees Celsius or greater. The method further involves removing the blocking layer from the dielectric material.

公开(公告)号：US20230416909A1

公开(公告)日：2023-12-28

申请号：US18336157

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Seshadri GANGULI ,  Gopi Chandran RAMACHANDRAN ,  Srinivas GANDIKOTA

IPC: C23C16/40 ,  C23C16/04

CPC classification number: C23C16/402 ,  C23C16/045

Abstract: Embodiments of the disclosure provide a method of forming a dielectric film in trenches of a substrate. The utilization of the ALD process and introduction of an inhibitor material onto features defining the trenches and into the trenches provides for suppression of forming the dielectric film near the top surface of the features in the trenches. The dielectric film is formed via an ALD process. The ALD process includes sequentially exposing the substrate to an inhibitor material, a first precursor, a purge gas, an oxygen-containing precursor, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the dielectric film.

公开(公告)号：US20190301011A1

公开(公告)日：2019-10-03

申请号：US16366570

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Prerna Sonthalia GORADIA ,  Robert Jan VISSER ,  Abhishek DUBE ,  Flora Fong-Song CHANG ,  Hua CHUNG

IPC: C23C16/44 ,  C23C16/52 ,  C23C16/48

Abstract: Embodiments of the disclosure may provide a method and apparatus for cleaning an epi-chamber at a low temperature so that residues are quickly eliminated from a surface of the epi-chamber after a performing a low temperature epitaxial deposition process. Some of the benefits of the present disclosure include flowing a chlorine containing gas to an improved epi-chamber having UV capability to chlorinate and quickly remove the epitaxial deposition residues at a low cleaning process temperature. As such, residues are decreased or removed from the epi-chamber such that further processing may be performed.

公开(公告)号：US20200283897A1

公开(公告)日：2020-09-10

申请号：US16800310

申请日：2020-02-25

Applicant: Applied Materials, Inc.

Inventor： Nitin DEEPAK ,  Suresh Chand SETH ,  Prerna Sonthalia GORADIA ,  Geetika BAJAJ ,  Darshan THAKARE ,  Jennifer Y. SUN ,  Gayatri NATU

IPC: C23C16/455 ,  C23C16/08 ,  C23C16/40 ,  C23C22/34

Abstract: Embodiments described herein provide a method of forming amorphous a fluorinated metal film. The method includes positioning an object in an atomic layer deposition (ALD) chamber having a processing region, depositing a metal-oxide containing layer on an object using an atomic layer deposition (ALD) process, depositing a metal-fluorine layer on the metal-oxide containing layer using an activated fluorination process, and repeating the depositing the metal-oxide containing layer and the depositing the metal-oxide containing layer until a fluorinated metal film with a predetermined film thickness is formed. The activated fluorination process includes introducing a first flow of a fluorine precursor (FP) to the processing region. The FP includes at least one organofluorine reagent or at least one fluorinated gas.

公开(公告)号：US20180308685A1

公开(公告)日：2018-10-25

申请号：US15951051

申请日：2018-04-11

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Prerna Sonthalia GORADIA ,  Robert Jan VISSER

IPC: H01L21/02 ,  C23C16/24 ,  C23C16/455 ,  C30B25/02 ,  C30B29/06

CPC classification number: H01L21/0262 ,  C23C16/24 ,  C23C16/45553 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (“SAM”) is used to achieve selective epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate to a self-assembled monolayer (“SAM”) forming molecule to selectively deposit a SAM film on an exposed dielectric material, wherein the substrate comprises the exposed dielectric material and an exposed silicon material. The SAM forming molecule is a chlorosilane molecule. The method further comprises epitaxially and selectively depositing a silicon-containing material layer on the exposed silicon material at a temperature of 400 degrees Celsius or lower. The method further comprises removing the SAM film from the exposed dielectric material.