A chip resistance element includes a base substrate having a first surface and a second surface opposing each other, two sides connecting the first surface and the second surface to each other, and two end surfaces connecting the first surface and the second surface to each other; a resistive layer disposed on the second surface; and a first terminal, a second terminal, and a third terminal disposed to be respectively connected to the resistive layer and to be separated from each other on the second surface. The third terminal having a second surface portion disposed between the first terminal and the second terminal on the second surface and a side portion connected to and disposed on one of the two sides of the base substrate.