Invention Application
- Patent Title: METHODS, APPARATUS AND SYSTEM FOR VERTICAL FINFET DEVICE WITH REDUCED PARASITIC CAPACITANCE
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Application No.: US15592172Application Date: 2017-05-10
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Publication No.: US20180331097A1Publication Date: 2018-11-15
- Inventor: Hui Zang , Rinus Tek Po Lee
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY GRAND CAYMAN
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY GRAND CAYMAN
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/8234 ; H01L21/764
Abstract:
A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.
Public/Granted literature
- US10204904B2 Methods, apparatus and system for vertical finFET device with reduced parasitic capacitance Public/Granted day:2019-02-12
Information query
IPC分类:
