公开(公告)号：US10134876B2

公开(公告)日：2018-11-20

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. Krishnan ,  Timothy J. McArdle ,  Rinus Tek Po Lee ,  Shishir K. Ray ,  Akshey Sehgal

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US10204904B2

公开(公告)日：2019-02-12

申请号：US15592172

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Rinus Tek Po Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/764

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.

公开(公告)号：US10211045B1

公开(公告)日：2019-02-19

申请号：US15878502

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rishikesh Krishnan ,  Joseph K. Kassim ,  Bharat V. Krishnan ,  Joseph F. Shepard, Jr. ,  Rinus Tek Po Lee ,  Yiheng Xu

IPC: H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

公开(公告)号：US10134739B1

公开(公告)日：2018-11-20

申请号：US15661058

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/115 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/28

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US20180331097A1

公开(公告)日：2018-11-15

申请号：US15592172

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Rinus Tek Po Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/764

CPC classification number: H01L27/0886 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.

公开(公告)号：US10896853B2

公开(公告)日：2021-01-19

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Wei Hong ,  Hui Zang ,  Hong Yu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

公开(公告)号：US10418365B2

公开(公告)日：2019-09-17

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US20190035791A1

公开(公告)日：2019-01-31

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/10814 ,  B82Y10/00 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/1248 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.