发明申请
- 专利标题: CAPACITOR BUILT-IN MULTILAYER WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF
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申请号: US16043603申请日: 2018-07-24
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公开(公告)号: US20180332707A1公开(公告)日: 2018-11-15
- 发明人: Tomoyuki Akahoshi , Daisuke Mizutani
- 申请人: FUJITSU LIMITED
- 申请人地址: JP Kawasaki-shi
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki-shi
- 主分类号: H05K1/16
- IPC分类号: H05K1/16 ; H05K1/11 ; H05K3/42 ; H01L23/498 ; H01L21/48 ; H01L49/02 ; H05K3/00 ; H01G4/12 ; H01G4/33
摘要:
A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
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