- 专利标题: Memory Circuit with Leakage Compensation
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申请号: US16112402申请日: 2018-08-24
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公开(公告)号: US20180366205A1公开(公告)日: 2018-12-20
- 发明人: Stephen Keith Heinrich-Barna , Raviprakash Suryanarayana Rao
- 申请人: Texas Instruments Incorporated
- 主分类号: G11C17/08
- IPC分类号: G11C17/08 ; G11C7/18 ; G11C16/04 ; G11C16/30 ; G11C16/26
摘要:
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
公开/授权文献
- US10593413B2 Memory circuit with leakage compensation 公开/授权日:2020-03-17