Invention Application
- Patent Title: PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION AND STRUCTURES RESULTING THEREFROM
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Application No.: US16069154Application Date: 2016-03-28
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Publication No.: US20190019748A1Publication Date: 2019-01-17
- Inventor: Charles H. WALLACE , Leonard P. GULER , Manish CHANDHOK , Paul A. NYHUS
- Applicant: Intel Corporation
- International Application: PCT/US2016/024553 WO 20160328
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/532 ; H01L21/768

Abstract:
Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.
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