公开(公告)号：US20240421201A1

公开(公告)日：2024-12-19

申请号：US18336323

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Thomas O’BRIEN ,  Charles H. WALLACE ,  Anindya DASGUPTA

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for creating flyover trench connectors within a transistor structure, where a first portion of the trench connector is electrically coupled with a first epitaxial structure and where a second portion of the trench connector extends above but is not electrically coupled with a second epitaxial structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20240395886A1

公开(公告)日：2024-11-28

申请号：US18202678

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Shengsi LIU ,  Sean PURSEL

IPC: H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having partial channel cap removal, and methods of fabricating integrated circuit structures having partial channel cap removal, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires. A dielectric channel cap has an opening over the stack of nanowires. A gate electrode is over and around the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires. A conductive tap is on the gate electrode and in the opening in the dielectric channel cap. A dielectric layer is on the gate electrode and laterally adjacent to the conductive tap.

公开(公告)号：US20240355903A1

公开(公告)日：2024-10-24

申请号：US18763777

申请日：2024-07-03

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Dax M. CRUM ,  Stephen M. CEA ,  Leonard P. GULER ,  Tahir GHANI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US20240113111A1

公开(公告)日：2024-04-04

申请号：US17956779

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Clifford ONG ,  Sukru YEMENICIOGLU ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696

Abstract: Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.

公开(公告)号：US20240113017A1

公开(公告)日：2024-04-04

申请号：US17958288

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Gurpreet SINGH ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76892 ,  H01L21/76837 ,  H01L23/5226

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug within a metal layer of a semiconductor device, where the plug is formed within a cavity that is created through the metal layer. The plug may extend through the metal layer and into a layer below the metal layer, which may be a layer that includes a dielectric and one or more electrical routing features. The plug may include an electrical insulator material. The cavity may be formed by placing a mask above the metal layer and performing an etch through the metal layer subsequently filled with a dielectric, where the plug will be tapered and wider at the top of the plug and become narrower as the plug continues through the metal layer and reaches the layer below the metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105716A1

公开(公告)日：2024-03-28

申请号：US17954206

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Mohit K. HARAN ,  Stephen M. CEA ,  Charles H. WALLACE ,  Tahir GHANI ,  Shengsi LIU ,  Saurabh ACHARYA ,  Thomas O'BRIEN ,  Nidhi KHANDELWAL ,  Marie T. CONTE ,  Prabhjot LUTHRA

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20230317787A1

公开(公告)日：2023-10-05

申请号：US17709374

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0886

Abstract: Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20230197780A1

公开(公告)日：2023-06-22

申请号：US17557932

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66742

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a fin with a first end and a second end. In an embodiment, a first dielectric covers the first end of the fin, and a second dielectric covers the second end of the fin. In an embodiment, a gate structure is over the first end of the fin, where the gate structure is on a top surface of the fin and a top surface of the first dielectric.

公开(公告)号：US20230095402A1

公开(公告)日：2023-03-30

申请号：US17485190

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

公开(公告)号：US20220416040A1

公开(公告)日：2022-12-29

申请号：US17357748

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Oleg GOLONZKA ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8234

Abstract: Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.