- 专利标题: MEMORY SYSTEM WITH LDPC DECODER AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND LDPC DECODER
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申请号: US16010026申请日: 2018-06-15
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公开(公告)号: US20190068220A1公开(公告)日: 2019-02-28
- 发明人: Naveen KUMAR , Aman BHATIA , Chenrong XIONG , Yu CAI , Fan ZHANG
- 申请人: SK Hynix Memory Solutions Inc.
- 主分类号: H03M13/11
- IPC分类号: H03M13/11 ; G06F11/10 ; G11C29/52 ; G06N3/08 ; G06N3/04
摘要:
A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder that may be included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.
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