Invention Application
- Patent Title: TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE
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Application No.: US16080824Application Date: 2016-04-01
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Publication No.: US20190088759A1Publication Date: 2019-03-21
- Inventor: SEUNG HOON SUNG , WILLY RACHMADY , JACK T. KAVALIEROS , HAN WUI THEN , MARKO RADOSAVLJEVIC
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US2016/025597 WO 20160401
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/423

Abstract:
Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.
Public/Granted literature
- US10784360B2 Transistor gate trench engineering to decrease capacitance and resistance Public/Granted day:2020-09-22
Information query
IPC分类: