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    TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE
    1.
    发明申请
    TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE 审中-公开

    公开(公告)号：US20200373403A1

    公开(公告)日：2020-11-26

    申请号：US16990219

    申请日：2020-08-11

    Applicant: INTEL CORPORATION

    Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

    Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

    LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE
    4.
    发明申请
    LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE 审中-公开

    公开(公告)号：US20200006330A1

    公开(公告)日：2020-01-02

    申请号：US16024076

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： AARON D. LILAK ,  ANH PHAN ,  EHREN MANNEBACH ,  CHENG-YING HUANG ,  STEPHANIE A. BOJARSKI ,  GILBERT DEWEY ,  ORB ACTON ,  WILLY RACHMADY

    IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L21/762

    Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    9.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200294998A1

    公开(公告)日：2020-09-17

    申请号：US16355195

    申请日：2019-03-15

    Applicant: INTEL CORPORATION

    Inventor： AARON D. LILAK ,  EHREN MANNEBACH ,  ANH PHAN ,  RICHARD E. SCHENKER ,  STEPHANIE A. BOJARSKI ,  WILLY RACHMADY ,  PATRICK R. MORROW ,  JEFFERY D. BIELEFELD ,  GILBERT DEWEY ,  HUI JAE YOO

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/532

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

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