Invention Application
- Patent Title: Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices
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Application No.: US15719686Application Date: 2017-09-29
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Publication No.: US20190103472A1Publication Date: 2019-04-04
- Inventor: Chao-Ching Cheng , Wei-Sheng Yun , I-Sheng Chen , Shao-Ming Yu , Tzu-Chiang Chen , Chih Chieh Yeh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L29/165 ; H01L21/8238 ; H01L27/092

Abstract:
A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
Public/Granted literature
- US10804367B2 Gate stacks for stack-fin channel I/O devices and nanowire channel core devices Public/Granted day:2020-10-13
Information query
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