In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.