公开(公告)号：US20190121462A1

公开(公告)日：2019-04-25

申请号：US15962529

申请日：2018-04-25

申请人： Atmel Corporation

发明人： Trond Jarle Pedersen ,  Torgeir Fenheim ,  Jan Rune Herheim ,  Stefan Markus Schabel

IPC分类号： G06F3/044 ,  G06F1/3234 ,  G06F3/041

CPC分类号： G06F3/044 ,  G06F1/3262 ,  G06F3/0416 ,  G06F2203/04107

摘要： In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.

公开(公告)号：US10466851B2

公开(公告)日：2019-11-05

申请号：US15962529

申请日：2018-04-25

申请人： Atmel Corporation

发明人： Trond Jarle Pedersen ,  Torgeir Fenheim ,  Jan Rune Herheim ,  Stefan Markus Schabel

IPC分类号： G06F3/041 ,  G06F3/044 ,  G06F1/3234

摘要： In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.

公开(公告)号：US09983748B2

公开(公告)日：2018-05-29

申请号：US15045834

申请日：2016-02-17

申请人： Atmel Corporation

发明人： Trond Jarle Pedersen ,  Torgeir Fenheim ,  Jan Rune Herheim ,  Stefan Markus Schabel

IPC分类号： G06F3/041 ,  G06F3/044 ,  G06F1/32

CPC分类号： G06F3/044 ,  G06F1/3262 ,  G06F3/0416 ,  G06F2203/04107

摘要： In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.

公开(公告)号：US20170235388A1

公开(公告)日：2017-08-17

申请号：US15045834

申请日：2016-02-17

申请人： Atmel Corporation

发明人： Trond Jarle Pedersen ,  Torgeir Fenheim ,  Jan Rune Herheim ,  Stefan Markus Schabel

IPC分类号： G06F3/044 ,  G06F3/041

CPC分类号： G06F3/044 ,  G06F1/3262 ,  G06F3/0416 ,  G06F2203/04107

摘要： In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.