- 专利标题： Semiconductor Packaging Structure and Process
-
申请号： US16222435申请日： 2018-12-17
-
公开(公告)号： US20190139817A1公开(公告)日： 2019-05-09
- 发明人: Kuan-Lin Ho , Chin-Liang Chen , Wei-Ting Lin , Yu-Chih Liu , Shih-Yen Lin
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号： H01L21/762
- IPC分类号： H01L21/762 ; H01L25/065 ; H01L23/00 ; H01L23/16 ; H01L21/683 ; H01L23/367 ; H01L21/56
摘要：
A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
信息查询
IPC分类:
