公开(公告)号：US09793242B2

公开(公告)日：2017-10-17

申请号：US14143895

申请日：2013-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Liu ,  Hai-Ming Chen ,  Wei-Ting Lin ,  Jing Ruei Lu ,  Tsung-Ding Wang

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/42

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/49827 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06548

摘要： A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.

公开(公告)号：US09142523B2

公开(公告)日：2015-09-22

申请号：US14087318

申请日：2013-11-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yu-Chih Liu ,  Chun-Cheng Lin ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Chin-Liang Chen ,  Shih-Yen Lin

IPC分类号： H01L23/10 ,  H01L23/28 ,  H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/367

CPC分类号： H01L23/293 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/29022 ,  H01L2224/29036 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier.

摘要翻译： 半导体器件包括载体，包括第一表面和第二表面的管芯，设置在载体的第二表面和管芯之间的多个第一导电凸块，其中管芯被翻转接合在载体上，并且模制件 在所述载体上并围绕所述模具，其中所述模制件包括设置在所述模具的所述第一表面上的凹部，从而留下所述第一表面的一部分被所述模制件覆盖。 此外，制造半导体器件的方法包括提供载体，在载体上翻转接合模具，在模具的第一表面和模具的第一表面内设置橡胶材料，并且形成围绕橡胶材料的模制品 并覆盖承运人。

公开(公告)号：US20150214128A1

公开(公告)日：2015-07-30

申请号：US14163000

申请日：2014-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yen Lin ,  Yu-Chih Liu ,  Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho

IPC分类号： H01L23/367 ,  H01L21/56 ,  H01L23/10

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/014

摘要： Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

摘要翻译： 本文公开了一种具有包括工件的成形密封环的装置，所述工件包括设置在基板的第一侧上的至少一个电介质层，设置在所述至少一个电介质层中的密封环，以及至少一个凹槽 密封环。 盖子设置在工件上方，工件延伸到盖中的凹部中，并且第一热界面材料（TIM）接触密封环和盖子，第一TIM延伸到至少一个凹槽中。 工件安装到包装托架上。 模具安装在工件的第一侧上并设置在凹部中。 第一底部填充物设置在模具下方，第二底部填充物设置在工件和包装载体之间。 第一TIM置于第一底部填充物和第二底部填充物之间。

公开(公告)号：US20150187734A1

公开(公告)日：2015-07-02

申请号：US14143895

申请日：2013-12-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Chih Liu ,  Hai-Ming Chen ,  Wei-Ting Lin ,  Jing Ruei Lu ,  Tsung-Ding Wang

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/49827 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06548

摘要： A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.

摘要翻译： 一种方法包括将第一器件管芯接合到封装衬底的顶表面上，并且在第一器件管芯和封装衬底上执行暴露模制。 至少第一器件裸片的下部被模制成模制材料。 模制材料的顶表面与第一器件裸片的顶表面平齐或高于第一器件裸片的顶表面。 在曝光模制之后，将第二器件裸片接合到第一器件裸片的顶表面上。 第二器件管芯通过第一器件管芯的半导体衬底中的穿硅通孔电耦合到第一器件管芯。

公开(公告)号：US10515941B2

公开(公告)日：2019-12-24

申请号：US15859097

申请日：2017-12-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Liu ,  Kuan-Lin Ho ,  Wei-ting Lin ,  Chin-Liang Chen ,  Jing Ruei Lu

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/14 ,  H01L23/15 ,  H01L23/367

摘要： Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.

公开(公告)号：US20170345708A1

公开(公告)日：2017-11-30

申请号：US15676326

申请日：2017-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Lin Ho ,  Chin-Liang Chen ,  Wei-Ting Lin ,  Yu-Chih Liu ,  Shih-Yen Lin

IPC分类号： H01L21/762 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/16 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L23/42 ,  H01L23/40 ,  H01L23/373 ,  H01L23/36 ,  H01L23/04

CPC分类号： H01L21/76251 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/04 ,  H01L23/16 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/40 ,  H01L23/4012 ,  H01L23/42 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/29109 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83493 ,  H01L2224/83862 ,  H01L2224/92122 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/0103 ,  H01L2924/05032 ,  H01L2924/0532 ,  H01L2924/0542 ,  H01L2924/05432 ,  H01L2924/15311 ,  H01L2924/1616 ,  H01L2924/16195 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/01006 ,  H01L2224/83 ,  H01L25/50 ,  H01L2924/00

摘要： A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

公开(公告)号：US20170271223A1

公开(公告)日：2017-09-21

申请号：US15613815

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yen Lin ,  Yu-Chih Liu ,  Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho

IPC分类号： H01L23/10 ,  H01L23/58 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/04

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/014

摘要： Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

公开(公告)号：US09735043B2

公开(公告)日：2017-08-15

申请号：US14137478

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Lin Ho ,  Chin-Liang Chen ,  Wei-Ting Lin ,  Yu-Chih Liu ,  Shih-Yen Lin

IPC分类号： H01L21/48 ,  H01L23/34 ,  H01L23/36 ,  H01L23/40 ,  H01L23/42 ,  H01L21/762 ,  H01L23/16 ,  H01L21/56 ,  H01L23/367 ,  H01L21/683 ,  H01L25/065 ,  H01L23/04 ,  H01L23/373 ,  H01L23/00

CPC分类号： H01L21/76251 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/04 ,  H01L23/16 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/40 ,  H01L23/4012 ,  H01L23/42 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/29109 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83493 ,  H01L2224/83862 ,  H01L2224/92122 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/0103 ,  H01L2924/05032 ,  H01L2924/0532 ,  H01L2924/0542 ,  H01L2924/05432 ,  H01L2924/15311 ,  H01L2924/1616 ,  H01L2924/16195 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/01006 ,  H01L2224/83 ,  H01L25/50 ,  H01L2924/00

摘要： A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

公开(公告)号：US09666556B2

公开(公告)日：2017-05-30

申请号：US14754260

申请日：2015-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Liu ,  Chien-Kuo Chang ,  Chi-Yang Yu ,  Jing Ruei Lu ,  Chih-Hao Lin

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/96 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/37655 ,  H01L2224/40225 ,  H01L2224/40499 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/8393 ,  H01L2224/8493 ,  H01L2224/84931 ,  H01L2224/84947 ,  H01L2224/92 ,  H01L2224/92222 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.

公开(公告)号：US20160379955A1

公开(公告)日：2016-12-29

申请号：US14754260

申请日：2015-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Liu ,  Chien-Kuo Chang ,  Chi-Yang Yu ,  Jing Ruei Lu ,  Chih-Hao Lin

IPC分类号： H01L23/00

CPC分类号： H01L24/96 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/37655 ,  H01L2224/40225 ,  H01L2224/40499 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/8393 ,  H01L2224/8493 ,  H01L2224/84931 ,  H01L2224/84947 ,  H01L2224/92 ,  H01L2224/92222 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.

摘要翻译： 集成电路（IC）封装包括第一衬底; 设置在所述第一基板上的第二基板; 多个连接器，设置在所述第一和第二基板之间，以使所述第一和第二基板电耦合; 限制层，设置在所述第一和第二基板上，使得在所述约束层和所述第一基板之间形成空腔; 以及设置在腔内并延伸穿过约束层的成型材料。 约束层具有顶表面和相对的底表面，并且模制材料从约束层的顶表面延伸到底表面。