Invention Application
- Patent Title: SEMICONDUCTOR DEVICES HAVING VERTICAL TRANSISTORS WITH ALIGNED GATE ELECTRODES
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Application No.: US16284843Application Date: 2019-02-25
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Publication No.: US20190189778A1Publication Date: 2019-06-20
- Inventor: Sungil PARK , Changhee KIM , Yunil LEE , Mirco CANTORO , Junggun YOU , Donghun LEE
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2017-0024948 20170224
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/40 ; H01L21/28 ; H01L29/10 ; H01L29/423 ; H01L29/06 ; H01L29/78

Abstract:
A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.
Public/Granted literature
- US10559673B2 Semiconductor devices having vertical transistors with aligned gate electrodes Public/Granted day:2020-02-11
Information query
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