Invention Application
- Patent Title: ERROR CORRECTION USING HIERARCHICAL DECODERS
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Application No.: US15958496Application Date: 2018-04-20
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Publication No.: US20190324848A1Publication Date: 2019-10-24
- Inventor: Paolo Amato , Marco Sforzin
- Applicant: Micron Technology, Inc.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/11 ; H03M13/29

Abstract:
Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
Public/Granted literature
- US10606694B2 Error correction using hierarchical decoders Public/Granted day:2020-03-31
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