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187 条记录 (耗时 0.034 秒)

    Drift compensation for codewords in memory
    1.
    发明授权
    Drift compensation for codewords in memory 有权

    公开(公告)号：US12087391B2

    公开(公告)日：2024-09-10

    申请号：US17948423

    申请日：2022-09-20

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

    IPC分类号： G11C7/10 ,  G11C11/56

    CPC分类号： G11C7/1063 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/5621

    摘要： Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. The circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. The circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a Pearson detector, and determine the originally programmed data of the codeword using the Pearson detector.

    Balancing data in memory
    2.
    发明授权
    Balancing data in memory 有权

    公开(公告)号：US12080350B2

    公开(公告)日：2024-09-03

    申请号：US17890912

    申请日：2022-08-18

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Riccardo Muzzetto

    IPC分类号： G11C11/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

    CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26

    摘要： The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

    Address scrambling by linear maps in Galois fields
    3.
    发明授权
    Address scrambling by linear maps in Galois fields 有权

    公开(公告)号：US12056061B2

    公开(公告)日：2024-08-06

    申请号：US17663121

    申请日：2022-05-12

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Federica Cresci

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F17/16

    CPC分类号： G06F12/1441 ,  G06F12/0238 ,  G06F12/1483 ,  G06F17/16

    摘要： Methods, systems, and devices for address scrambling by linear maps in Galois fields are described. For instance, a device may determine a bijective matrix based on a power up condition. In some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. In some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. The device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.

    Providing multiple error correction code protection levels in memory
    4.
    发明授权
    Providing multiple error correction code protection levels in memory 有权

    公开(公告)号：US12039176B2

    公开(公告)日：2024-07-16

    申请号：US17952614

    申请日：2022-09-26

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

    摘要： The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

    BALANCING DATA IN MEMORY
    5.
    发明公开
    BALANCING DATA IN MEMORY 审中-公开

    公开(公告)号：US20240062824A1

    公开(公告)日：2024-02-22

    申请号：US17890912

    申请日：2022-08-18

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Riccardo Muzzetto

    IPC分类号： G11C16/10 ,  G11C16/08 ,  G11C16/26

    CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26

    摘要： The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

    NON-CACHED DATA TRANSFER
    7.
    发明公开
    NON-CACHED DATA TRANSFER 审中-公开

    公开(公告)号：US20240005010A1

    公开(公告)日：2024-01-04

    申请号：US18215462

    申请日：2023-06-28

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Paolo Amato

    IPC分类号： G06F21/60 ,  G06F21/31 ,  G06F11/10

    CPC分类号： G06F21/602 ,  G06F21/31 ,  G06F11/1068

    摘要： A memory controller can operate to provide various data protection schemes without a need of a cache. A unit of data transfer between the memory controller and memory devices can correspond to a size of data corresponding to a host read and/or write command. The memory controller operating without a cache can still ensure data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

    ADDRESS SCRAMBLING BY LINEAR MAPS IN GALOIS FIELDS
    8.
    发明公开
    ADDRESS SCRAMBLING BY LINEAR MAPS IN GALOIS FIELDS 审中-公开

    公开(公告)号：US20230367721A1

    公开(公告)日：2023-11-16

    申请号：US17663121

    申请日：2022-05-12

    申请人： Micron Technology, Inc.

    发明人： Marco Sforzin ,  Federica Cresci

    IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F17/16

    CPC分类号： G06F12/1441 ,  G06F12/1483 ,  G06F12/0238 ,  G06F17/16

    摘要： Methods, systems, and devices for address scrambling by linear maps in Galois fields are described. For instance, a device may determine a bijective matrix based on a power up condition. In some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. In some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. The device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.

    Balancing data for storage in a memory device
    9.
    发明授权
    Balancing data for storage in a memory device 有权

    公开(公告)号：US11733913B2

    公开(公告)日：2023-08-22

    申请号：US17677586

    申请日：2022-02-22

    申请人： Micron Technology, Inc.

    发明人： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0655 ,  G06F3/0602 ,  G06F3/0673

    摘要： Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.