- 专利标题： INTEGRATED CIRCUIT LAYOUT METHOD, DEVICE, AND SYSTEM
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申请号： US16204678申请日： 2018-11-29
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公开(公告)号： US20200006316A1公开(公告)日： 2020-01-02
- 发明人: Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 主分类号： H01L27/02
- IPC分类号： H01L27/02 ; G06F17/50 ; H01L27/092
摘要：
A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.
公开/授权文献
- US10741540B2 Integrated circuit layout method and device 公开/授权日：2020-08-11
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