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1.发明申请公开(公告)号：US20200058586A1
公开(公告)日：2020-02-20
申请号：US16530808
申请日：2019-08-02
发明人： Tai-Pen GUO , Li-Chun TIEN , Chien-Ying CHEN , Lee-Chung LU
IPC分类号： H01L23/522 , G06F17/50
摘要： A method (of generating a layout diagram) includes: generating one or more first conductive patterns representing corresponding conductive material in the first metallization layer, long axes of the first conductive patterns extending substantially in a first direction; generating a first deep via pattern representing corresponding conductive material in each of the second via layer, the first metallization layer, and the first via layer; relative to the first direction and a second direction substantially perpendicular to the first direction, aligning the first deep via pattern to overlap a corresponding component pattern representing conductive material included in an electrical path of a terminal of a corresponding transistor in the transistor layer; and configuring a size of the first deep via pattern in the first direction to be substantially less than a permissible minimum length of a conductive pattern in the first metallization layer.
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公开(公告)号：US20230378159A1
公开(公告)日：2023-11-23
申请号：US18362960
申请日：2023-08-01
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , H01L27/092 , G06F30/392
CPC分类号： H01L27/0207 , H01L27/092 , G06F30/392
摘要： An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.
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公开(公告)号：US20210384121A1
公开(公告)日：2021-12-09
申请号：US17410782
申请日：2021-08-24
发明人： Ta-Pen GUO , Chien-Ying CHEN , Li-Chun TIEN , Lee-Chung LU
IPC分类号： H01L23/522 , G06F30/394
摘要： A method (of manufacturing a semiconductor device) includes: forming via structures in a first via layer over a transistor layer; forming a first via structure of a first deep via arrangement in the first via layer; forming conductive segments in a first metallization layer over the first via layer; forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value and which is included in the first deep via arrangement; and forming via structures in a second via layer over the first metallization layer, including forming a first via structure of the first deep via arrangement in the second via layer.
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公开(公告)号：US20200350307A1
公开(公告)日：2020-11-05
申请号：US16936175
申请日：2020-07-22
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , H01L27/092 , G06F30/392
摘要： A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.
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公开(公告)号：US20230354591A1
公开(公告)日：2023-11-02
申请号：US18346700
申请日：2023-07-03
发明人： Meng-Sheng CHANG , Chien-Ying CHEN , Chia-En HUANG , Yih WANG
IPC分类号： H10B20/20 , G06F30/392 , H01L23/522 , H01L23/528
CPC分类号： H10B20/20 , G06F30/392 , H01L23/5226 , H01L23/528
摘要： A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.
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公开(公告)号：US20230163066A1
公开(公告)日：2023-05-25
申请号：US18156711
申请日：2023-01-19
发明人： Ta-Pen GUO , Chien-Ying CHEN , Li-Chun TIEN , Lee-Chung LU
IPC分类号： H01L23/522 , G06F30/394
CPC分类号： H01L23/5226 , G06F30/394
摘要： A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.
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公开(公告)号：US20220271025A1
公开(公告)日：2022-08-25
申请号：US17740328
申请日：2022-05-09
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , H01L27/092 , G06F30/392
摘要： An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction.
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公开(公告)号：US20200006316A1
公开(公告)日：2020-01-02
申请号：US16204678
申请日：2018-11-29
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , G06F17/50 , H01L27/092
摘要： A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.
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9.发明公开公开(公告)号：US20240098988A1
公开(公告)日：2024-03-21
申请号：US18521375
申请日：2023-11-28
发明人： Chien-Ying CHEN , Yao-Jen YANG
IPC分类号： H10B20/20 , G06F30/392
CPC分类号： H10B20/20 , G06F30/392
摘要： A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.
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公开(公告)号：US20240096789A1
公开(公告)日：2024-03-21
申请号：US18524621
申请日：2023-11-30
发明人： Meng-Sheng CHANG , Chien-Ying CHEN , Yao-Jen YANG
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L21/76892
摘要： An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.
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