Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.