A programmable decoder (201) includes a counter (204A) whose count value increases for each clock; an address decoder (205A) for converting the count value into an address; a storage (251A) storing a table defining data according to the address converted from the count value; and a latch unit (207) for latching the data according to the address output from the storage (251A). A variable driver (202) includes a plurality of MOS transistors (208), (209), (210). The latch unit (207A) has outputs connected to control electrodes of a plurality of MOS transistors (208), (209), (210). The table defines a plurality of data items in the table so that the driving force of the variable driver (202) increases with an increase of the count value. A counter (20A) updates the count value while the arm control signal is being activated.