Invention Application
- Patent Title: Reordering avoidance for flows during transition between slow-path handling and fast-path handling
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Application No.: US16202132Application Date: 2018-11-28
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Publication No.: US20200167192A1Publication Date: 2020-05-28
- Inventor: Eitan Hirshberg , Ariel Shahar , Najeeb Darawshy , Omri Kahalon
- Applicant: Mellanox Technologies, Ltd.
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06F9/38 ; G06F9/30

Abstract:
A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.
Public/Granted literature
- US10824469B2 Reordering avoidance for flows during transition between slow-path handling and fast-path handling Public/Granted day:2020-11-03
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