Invention Application
- Patent Title: DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
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Application No.: US16690743Application Date: 2019-11-21
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Publication No.: US20200168288A1Publication Date: 2020-05-28
- Inventor: Ely Tsern , Frederick A Ware , Suresh Rajan , Thomas Vogelsang
- Applicant: Rambus Inc.
- Main IPC: G11C29/24
- IPC: G11C29/24 ; G11C29/50 ; G06F11/10

Abstract:
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
Public/Granted literature
- US11011248B2 DRAM retention test method for dynamic error correction Public/Granted day:2021-05-18
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