公开(公告)号：US12190974B2

公开(公告)日：2025-01-07

申请号：US18138661

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20240290414A1

公开(公告)日：2024-08-29

申请号：US18515681

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewon Kim ,  Sanghee Kang ,  Kiho Hyun ,  Taeyun Kim

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/24

CPC classification number: G11C29/44 ,  G11C29/12015 ,  G11C29/24

Abstract: A method of testing a repair circuit of a memory device. The method may include storing first addresses in a first register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses, storing test addresses in a second register of the repair circuit, wherein the test addresses are provided from a test host, outputting hit signals by comparing bit values of the addresses stored in the first register with bit values of the addresses stored in the second register, outputting repair enable signals based on the hit signals, and determining a status of a path where the repair enable signals are generated based on logic levels of the repair enable signals.

公开(公告)号：US20230298683A1

公开(公告)日：2023-09-21

申请号：US17654998

申请日：2022-03-16

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Kangguo Cheng ,  Ruilong Xie

IPC: G11C29/44 ,  G11C29/02 ,  G11C29/24 ,  G11C29/12 ,  G11C11/16

CPC classification number: G11C29/4401 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C29/024 ,  G11C29/1201 ,  G11C29/24 ,  G11C2029/1802 ,  G11C2029/4402

Abstract: Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

公开(公告)号：US11626185B2

公开(公告)日：2023-04-11

申请号：US17723200

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C8/12 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US11551780B2

公开(公告)日：2023-01-10

申请号：US15996005

申请日：2018-06-01

Applicant: SK hynix Inc.

Inventor： Dong Keun Kim

IPC: G11C16/06 ,  G11C29/00 ,  G11C29/44 ,  G11C29/24

Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

公开(公告)号：US11380416B2

公开(公告)日：2022-07-05

申请号：US17233689

申请日：2021-04-19

Applicant: SK hynix Inc.

Inventor： Eun Jae Ock

IPC: G11C29/42 ,  G11C29/24 ,  G11C29/02 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16 ,  G11C29/12

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a memory block including a plurality of pages. When a sudden power off is detected in which power supplied to the memory device is abnormally interrupted during a normal program operation on one page among the plurality of pages, the memory controller may control the memory device to perform a dummy program operation on a selected page among the plurality of pages after the sudden power-off. The memory controller may control the memory device to perform the normal program operation and the dummy program operation by using an Incremental Step Pulse Program (ISPP) method. The memory controller may control the memory device to perform the dummy program operation in a smaller number of program loops as compared with the normal program operation.

公开(公告)号：US11380415B2

公开(公告)日：2022-07-05

申请号：US17130250

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/24 ,  G11C29/44

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US11373724B2

公开(公告)日：2022-06-28

申请号：US16624347

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Alberto Troia ,  Antonino Mondello

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/24 ,  G11C29/44

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

公开(公告)号：US20210313004A1

公开(公告)日：2021-10-07

申请号：US17164946

申请日：2021-02-02

Applicant: FUJITSU LIMITED

Inventor： Yoshitsugu Goto

IPC: G11C29/44 ,  G11C29/24 ,  G11C29/00 ,  G11C29/10 ,  G11C7/10

Abstract: A memory includes a plurality of memory dies that includes a plurality of memory regions stacked on each other, the plurality of memory regions including a memory cell region that stores data and a redundant cell region that stores data as an alternative when a part of the memory cell region fails; a multiplexer that outputs data supplied to a local memory region or data supplied to another memory region to the redundant cell region of the local memory region on a basis of an input selection signal from outside; and a selector that outputs data output from the redundant cell region of the local memory region or data output from the redundant cell region of the other memory region to a data terminal of the local memory region on a basis of an output selection signal from outside.

公开(公告)号：US20210295945A1

公开(公告)日：2021-09-23

申请号：US16824362

申请日：2020-03-19

Applicant: SanDisk Technologies LLC

Inventor： Siddarth Naga Murty Bassa ,  Yenlung Li

IPC: G11C29/00 ,  G11C29/24 ,  G11C29/44

Abstract: An apparatus includes nonvolatile memory cells arranged in columns including a plurality of redundant columns with control circuits coupled to the nonvolatile memory cells. The control circuits are configured to maintain an ordered list of bad columns replaced by redundant columns. The control circuits are configured to detect an out-of-order entry in the ordered list of bad columns replaced by redundant columns.