Invention Application
- Patent Title: SEMICONDUCTOR WAFER FAULT ANALYSIS SYSTEM AND OPERATION METHOD THEREOF
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Application No.: US16599733Application Date: 2019-10-11
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Publication No.: US20200175665A1Publication Date: 2020-06-04
- Inventor: Min-Chul PARK , Ami MA , Jisu RYU , Changwook JEONG
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2311aadc
- Main IPC: G06T7/00
- IPC: G06T7/00 ; H01L21/67 ; G01N21/956 ; G06T5/00 ; G01N21/95

Abstract:
A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.
Public/Granted literature
- US11741596B2 Semiconductor wafer fault analysis system and operation method thereof Public/Granted day:2023-08-29
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