Invention Application
- Patent Title: LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION
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Application No.: US16203816Application Date: 2018-11-29
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Publication No.: US20200176258A1Publication Date: 2020-06-04
- Inventor: Hui Zang , David P. Brunco
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/8234 ; H01L21/3213 ; H01L27/088 ; H01L29/49 ; H01L29/06

Abstract:
Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.
Public/Granted literature
- US10727067B2 Late gate cut using selective conductor deposition Public/Granted day:2020-07-28
Information query
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