Aspects of the disclosure are directed to isolation in integrated circuits. In accordance with one aspect, implementing a complementary metal oxide semiconductor (CMOS) isolation in an integrated circuit (IC) includes etching an interlayer dielectric (ILD) between two of a plurality of gates in a first section of an integrated circuit (IC); etching a semiconductor substrate to form a trench within an active region in the first section; and filling the trench with an insulator in the first section and planarizing the integrated circuit (IC).