利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.014 秒)

    SUBTRACTIVE DAMASCENE FORMATION OF HYBRID INTERCONNECTIONS
    2.
    发明申请
    SUBTRACTIVE DAMASCENE FORMATION OF HYBRID INTERCONNECTIONS 有权

    公开(公告)号：US20220262723A1

    公开(公告)日：2022-08-18

    申请号：US17176969

    申请日：2021-02-16

    申请人： QUALCOMM Incorporated

    发明人： Junjing BAO ,  John Jianhong ZHU ,  Haining YANG

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

    摘要： An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material.

    TRANSISTOR WITH INSULATOR
    3.
    发明申请
    TRANSISTOR WITH INSULATOR 有权

    公开(公告)号：US20210280684A1

    公开(公告)日：2021-09-09

    申请号：US16812292

    申请日：2020-03-07

    申请人： QUALCOMM Incorporated

    发明人： Ye LU ,  Haining YANG ,  Junjing BAO

    IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

    摘要： A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

    GATE-ALL-AROUND (GAA) AND FIN FIELD-EFFECT TRANSISTOR (FINFET) HYBRID STATIC RANDOM-ACCESS MEMORY (SRAM)
    4.
    发明申请
    GATE-ALL-AROUND (GAA) AND FIN FIELD-EFFECT TRANSISTOR (FINFET) HYBRID STATIC RANDOM-ACCESS MEMORY (SRAM) 有权

    公开(公告)号：US20210020643A1

    公开(公告)日：2021-01-21

    申请号：US16511153

    申请日：2019-07-15

    申请人： QUALCOMM Incorporated

    发明人： Haining YANG

    IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

    摘要： Certain aspects of the present disclosure generally relate to a static random-access memory (SRAM) implemented using both a gate-all-around (GAA)-type transistor and a fin field-effect transistor (FinFET). For example, certain aspects are directed to an SRAM memory cell having a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor, and a pass-gate (PG) transistor coupled between a bit line of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell. In certain aspects, at least one of the PU transistor, the PD transistor, or the PG transistor comprises a GAA transistor, and at least another one of the PU transistor, the PD transistor, or the PG transistor comprises a FinFET.

    FINFET DEVICE AND METHOD OF MAKING THE SAME
    5.
    发明申请
    FINFET DEVICE AND METHOD OF MAKING THE SAME 有权
    FINFET器件及其制造方法

    公开(公告)号：US20170040324A1

    公开(公告)日：2017-02-09

    申请号：US14817441

    申请日：2015-08-04

    申请人： QUALCOMM Incorporated

    发明人： Haining YANG ,  Yanxiang LIU

    IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8238

    CPC分类号： H01L27/0924 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7845

    摘要： A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

    摘要翻译： 根据这里的一些示例的finFET器件可以包括有源鳍元件上方的有源栅极元件和部分地断开有源栅极元件的虚设鳍元件。 在另一示例中，与有源栅极元件相邻的伪栅极元件包含部分地断开伪栅极元件的虚设鳍元件。 在另一个示例中，第一虚拟翅片元件部分地中断有源栅极元件，并且第二虚设鳍元件部分地断开伪栅极元件。 在另一个示例中，虚拟翅片元件具有与活动翅片元件相同的材料。 在另一个示例中，虚拟鳍片元件部分地打破栅极元件，但是不像活性鳍片元件那样延伸到衬底。

    DOUBLE DIFFUSION BREAK GATES FULLY OVERLAPPING FIN EDGES WITH INSULATOR REGIONS
    8.
    发明申请
    DOUBLE DIFFUSION BREAK GATES FULLY OVERLAPPING FIN EDGES WITH INSULATOR REGIONS 有权

    公开(公告)号：US20210359108A1

    公开(公告)日：2021-11-18

    申请号：US16875668

    申请日：2020-05-15

    申请人： QUALCOMM Incorporated

    发明人： Haining YANG ,  Xia LI ,  Bin YANG

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234

    摘要： Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure.