An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.