- 专利标题: APPARATUS AND METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT
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申请号: US16353409申请日: 2019-03-14
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公开(公告)号: US20200242190A1公开(公告)日: 2020-07-30
- 发明人: John L. McCollum , Jonathan W. Greene , Gregory William Bakker
- 申请人: Microsemi SoC Corp.
- 主分类号: G06F17/16
- IPC分类号: G06F17/16 ; H03K19/177 ; G06N3/04
摘要:
A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
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