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    Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
    2.
    发明授权
    Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit 有权

    公开(公告)号：US11023559B2

    公开(公告)日：2021-06-01

    申请号：US16353409

    申请日：2019-03-14

    申请人： Microsemi SoC Corp.

    发明人： John L. McCollum ,  Jonathan W. Greene ,  Gregory William Bakker

    IPC分类号： G06F17/16 ,  G06G7/161 ,  G06G7/22 ,  G06N3/04 ,  G06N3/063

    摘要： A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.

    FPGA math block with dedicated connections
    5.
    发明授权
    FPGA math block with dedicated connections 有权

    公开(公告)号：US10361702B2

    公开(公告)日：2019-07-23

    申请号：US16177244

    申请日：2018-10-31

    申请人： Microsemi SoC Corp.

    发明人： Jonathan W. Greene ,  Fei Li

    IPC分类号： H03K19/177 ,  G06F7/544

    摘要： An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.

    METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT
    8.
    发明申请
    METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT 有权

    公开(公告)号：US20210232658A1

    公开(公告)日：2021-07-29

    申请号：US17232075

    申请日：2021-04-15

    申请人： Microsemi SoC Corp.

    发明人： John L. McCollum ,  Jonathan W. Greene ,  Gregory William Bakker

    IPC分类号： G06F17/16 ,  G06N3/04 ,  G06G7/161 ,  G06G7/22

    摘要： A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.

    APPARATUS AND METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT
    10.
    发明申请
    APPARATUS AND METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200242190A1

    公开(公告)日：2020-07-30

    申请号：US16353409

    申请日：2019-03-14

    申请人： Microsemi SoC Corp.

    发明人： John L. McCollum ,  Jonathan W. Greene ,  Gregory William Bakker

    IPC分类号： G06F17/16 ,  H03K19/177 ,  G06N3/04

    摘要： A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.