Invention Application
- Patent Title: SPECULATIVE DRAM READ, IN PARALLEL WITH CACHE LEVEL SEARCH, LEVERAGING INTERCONNECT DIRECTORY
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Application No.: US16424452Application Date: 2019-05-28
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Publication No.: US20200301838A1Publication Date: 2020-09-24
- Inventor: Vikas SINHA , Hien LE , Tarun NAKRA , Yingying TIAN , Apurva PATEL , Omar TORRES
- Applicant: Samsung Electronics Co., Ltd.
- Main IPC: G06F12/0831
- IPC: G06F12/0831 ; G06F12/0868 ; G06F11/07
Abstract:
According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.
Public/Granted literature
- US11055221B2 Speculative DRAM read, in parallel with cache level search, leveraging interconnect directory Public/Granted day:2021-07-06
Information query
IPC分类:
