SPECULATIVE DRAM READ, IN PARALLEL WITH CACHE LEVEL SEARCH, LEVERAGING INTERCONNECT DIRECTORY

    公开(公告)号:US20200301838A1

    公开(公告)日:2020-09-24

    申请号:US16424452

    申请日:2019-05-28

    Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Patent Agency Ranking